Serial interfaces play an important role in high-speed chip-to-chip signaling. By transferring serialized data along a serial data path, or link, chip pin counts may be minimized while increasing data rates between the chips. While numerous serial protocols exist to enable transmission and receipt of high-speed packet data, very few adequately address power issues that may arise during data reception.
For example, many protocols employ data encoding algorithms to ensure a minimum edge transition density for the serial data stream. This is often provided to ensure that the receiver circuitry maintains a locked condition in terms of timing for proper data reception. During intervals of little to no real data transmission, “idle” control packets are often inserted into the packet stream and sent to satisfy the edge transition density requirements.
Internal to the receiver, as the packets are received, the real data words and the idle control words are often processed with the same circuitry. Although the idle control words may have some value if carrying error correction and flow control information, generally speaking, idle words have little-to-no “data” value. Unfortunately, since the same circuitry processes the data and idle words in the receiver, significant power consumption may occur during extended periods of real data inactivity (during peak idle packet activity).
Thus, the need exists for a serial data method and apparatus that minimizes power consumption for a serial link while still providing signal locking capabilities at the receiver.
Like reference numerals refer to corresponding parts throughout the drawing figures.